LEC-08 - 08 Combinational Testbenches 3/9/2010 Testbenches...

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08 Combinational Testbenches 3/9/2010 © Copyright Kenneth Short 2003, 2006 1 3/9/2010 © Copyright Kenneth Short 2003, 2006 1 Testbenches for Combinational Systems Prof. Ken Short 3/9/2010 © Copyright Kenneth Short 2003, 2006 2 VHDL Testbenches ± With VHDL you use the same language used to write a design description to write a test bench program. ± A testbench is a top-level design entity that has a mixed architecture. ± The description to be verified is instantiated as a component in the test bench’s architecture
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08 Combinational Testbenches 3/9/2010 © Copyright Kenneth Short 2003, 2006 2 3/9/2010 © Copyright Kenneth Short 2003, 2006 3 VHDL Testbenches (cont.) ± The design description is usually called the unit under test (UUT) ± UUT inputs and outputs can be viewed as waveforms ± The testbench can also automatically compare the UUT output values with expected values. ± Since a testbench is only simulated, not synthesized, the full range of VHDL language constructs and features can be used. 3/9/2010 © Copyright Kenneth Short 2003, 2006 4 Relationship of UUT to Testbench a sum carry_out b Testbench a_tb b_tb sum_tb carry_out_tb stimuli generation output verification
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08 Combinational Testbenches 3/9/2010 © Copyright Kenneth Short 2003, 2006 3 3/9/2010 © Copyright Kenneth Short 2003, 2006 5 Testbench Using Projected Waveforms library ieee; use ieee.std_logic_1164. all ; entity testbench is -- test bench entity has no ports end testbench; architecture waveform of testbench is -- Stimulus signals - mapped to the input and inout ports of UUT signal a_tb, b_tb : std_logic; -- Observed signals - mapped to the output ports of UUT signal sum_tb, carry_out_tb : std_logic; 3/9/2010 © Copyright Kenneth Short 2003, 2006 6 Testbench Using Projected Waveforms (cont.) begin -- Unit Under Test port map UUT : entity half_adder port map (a => a_tb, b => b_tb, sum => sum_tb, carry_out => carry_out_tb ); -- Signal assignment statements specifying input signal values a_tb <= '0', '1' after 40 ns; b_tb <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; end waveform;
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08 Combinational Testbenches 3/9/2010 © Copyright Kenneth Short 2003, 2006 4 3/9/2010 © Copyright Kenneth Short 2003, 2006 7 Testbench Declaration Part ± UUT component half_adder is declared ± UUT is instantiated in the statement part of the architecture body ± Local signals a_tb, b_tb, sum_tb, and carry_out_tb used to connect the UUT to the testbench ± Testbench assigns values to or observes the values of these local signals. 3/9/2010 © Copyright Kenneth Short 2003, 2006 8 Signal Assignment Syntax [ label: ] target <= value_expression [ after time_expression] {, value_expression [ after time_expression]}; target ::= name | aggregate
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08 Combinational Testbenches 3/9/2010 © Copyright Kenneth Short 2003, 2006 5 3/9/2010 © Copyright Kenneth Short 2003, 2006 9 Single Process Testbench ± A single process test bench applies a stimulus to the UUT, waits an appropriate length of time, and then checks the outputs of the UUT
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This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

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LEC-08 - 08 Combinational Testbenches 3/9/2010 Testbenches...

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