LEC-07 - 07 Event Driven Simulation 2/22/2010 Event Driven...

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07 Event Driven Simulation 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short 1 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Event Driven Simulation Prof. Ken Short 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Event Driven Simulation ± Simulation is the process of conducting experiments with a model of a system for the purpose of understanding or verifying the operation of the actual system. ± VHDL simulators are event driven simulators, also known as discrete event simulators. ± An event driven simulator performs three steps in simulating a description: ² elaboration ² initialization ² execution of simulation cycles
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07 Event Driven Simulation 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short 2 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Elaboration ± Elaboration is the expansion of a design description to build a model in the computer’s memory for simulation. ± This model consists of a network of simulation processes. ± A simulation process is similar to a VHDL process. ± During elaboration, the hierarchical structure of the description is flattened until the entire design is described behaviorally. 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Elaboration (cont.) ± Elaboration starts with the design’s top-level design entity. ± The top-level design entity may consist of component instantiation statements, concurrent signal assignment statements, and process statements. ± Elaboration converts each of these concurrent statements into a corresponding simulation process.
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07 Event Driven Simulation 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short 3 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Converting Processes and Signal Assignment Statements ± A process statement is already a behavioral description, so no conversion is needed for a process. ± A concurrent signal assignment statement is also a behavioral description. A concurrent signal assignment statement has an implied sensitivity list that includes all the signals on the right-hand side of the signal assignment symbol. 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Converting Components to Simulation Processes ± Only architectures containing components are not inherently behavioral. ± Each component instance in the top level design entity is replaced by its entity/architecture pair. ± If lower level architecture contains component instances they are replaced by their entity/architecture pair. ± Replacement continues until all components are ultimately replaced by entity/architecture pairs that have purely behavioral architectures.
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07 Event Driven Simulation 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short 4 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Example Circuit for Simulation uut/u0 testbench tb a f f a u0 ckt 2/22/2010 © Copyright 2003, 2006 Kenneth L. Short Not Gate Design Entity library ieee; use ieee.std_logic_1164. all ; entity not_gate is -- not gate entity port (x : in std_logic; o: out std_logic); end ; architecture dataflow of not_gate is -- not gate architecture begin o< = not x; end
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This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

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LEC-07 - 07 Event Driven Simulation 2/22/2010 Event Driven...

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