# LEC-05 - 05 Dataflow Architecture Dataflow Combinational...

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05 Dataflow Architecture © Copyright 2003, 2005, 2006 Kenneth L. Short 1 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 1 Dataflow Combinational Design Ken Short 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 2 Logical Operators ± not, and, or, nand, nor, xor, xnor ± not is highest precedence ± All other logical operators are same (and lowest) precedence

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05 Dataflow Architecture © Copyright 2003, 2005, 2006 Kenneth L. Short 2 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 3 Precedence ± Use parenthesis to force precedence ² Cannot write c <= a and not b or not a and b; ² When you mean c <= (a and not b) or ( not a and b); 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 4 Associative and Non-associative Logical Operators ± Operators and, or, xor, and xnor are associative ² For example, we can write: f <= a and b and c; ± Operators nand and nor are not associative ² For example, we cannot write: f <= a nand b nand c;
05 Dataflow Architecture © Copyright 2003, 2005, 2006 Kenneth L. Short 3 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 5 Array Logical Operations ± Logical operators can operate on specific elements by indexing the elements entity and_vector1 is port (x,y : in std_logic_vector(3 downto 0); f : out std_logic_vector(3 downto 0)); end and_vector1; architecture dataflow1 of and_vector1 is begin f(3) <= x(3) and y(3); f(2) <= x(2) and y(2); f(1) <= x(1) and y(1); f(0) <= x(0) and y(0); end dataflow1; 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 6 Array Logical Operations (cont.) ± Logical operations can be applied to entire arrays of the same length ± Matching of operand elements is positional starting from the leftmost position architecture dataflow2 of and_vector1 is begin f <= x and y; end dataflow2;

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05 Dataflow Architecture © Copyright 2003, 2005, 2006 Kenneth L. Short 4 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 7 The Matching of Array Elements entity and_vector2 is port (x : in std_logic_vector(3 downto 0); y : in std_logic_vector(0 to 3); f : out std_logic_vector(3 downto 0)); end and_vector2; architecture dataflow1 of and_vector2 is begin f <= x and y; end dataflow1; 2/8/2009 © Copyright 2003, 2005, 2006 Kenneth L. Short 8 Matching Array Elements (cont.) ± Matching of operand elements is positional starting from the leftmost position architecture dataflow2 of and_vector2 is begin f(3) <= x(3) and y(0); f(2) <= x(2) and y(1); f(1) <= x(1) and y(2); f(0) <= x(0) and y(3); end dataflow2;

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LEC-05 - 05 Dataflow Architecture Dataflow Combinational...

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