LEC-04 - 04 Signals and Data Types 1/16/2010 Signals and...

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04 Signals and Data Types 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 1 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 1 Signals and Data Types Ken Short 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 2 VHDL Objects ± An object is a named item used to represent or store data ± Object class represents the nature of an object and how it is used ± Four object classes ² Signal: has current and future values ² Constant: has a single constant value ² Variable: has a single current value ² File: has a sequence of values
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04 Signals and Data Types 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 2 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 3 Object Type ± Type defines the set of values and object can have and the valid operations on the object ± Determines storage requirements in the simulator ± Classes of types ² Scalar: has a single indivisible value ² Composite: a collection of elements each with a value ² Access: similar to a pointer ² File: provides access to files ² Protected: provides atomic and exclusive access to variables accessible to multiple processes 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 4 Strong Typing ± VHDL is a strongly typed language with strictly enforced type rules ± If we mix different types or exceed a type’s range of values, the compiler or simulator generates an error message ± For example, the integer value 0, the real number 0.0, and the bit value ‘0’ are not the same type, and, therefore, are not the same ± Strong typing makes it easier for a compiler to detect errors
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04 Signals and Data Types 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 3 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 5 Signal Declarations ± Signals are analogous to wires ± Ports are signals declared in the entity declaration (they have a direction) ± Local signals are declared in the architecture body (they do not have a direction) 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 6 Comparator Logic Diagram x y u1 u2 u3 u4 u5 s1 s2 s3 s4 eq
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04 Signals and Data Types 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 4 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 7 Comparator – Dataflow – no local signals library ieee; use ieee.std_logic_1164. all ; entity compare is port (x, y: in std_logic; eq: out std_logic); end compare; architecture dataflow of compare is begin eq <=( not x and not y) or (x and y); end dataflow; 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 8 Comparator – Dataflow – Local Signals library ieee; use ieee.std_logic_1164. all ; entity compare is port (x, y: in std_logic; eq: out std_logic); end compare; architecture dataflow2 of compare is signal x_bar, y_bar: std_logic; begin x_bar <= not x; y_bar <= not y; eq <=(x_bar and y_bar) or (x and y); end dataflow2;
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04 Signals and Data Types 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 5 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 9 Scalar Types Enumeration Types bit (chap. 3) boolean (chap. 4) integer types integer (chap 12) physical types time floating types real character (chap. 3) severity_level (chap. 7) file_open_kind (chap. 16) file_open_status (chap. 16) discrete numeric predefined Scalar Types 1/16/2010 © Copyright 2005, 2006 Kenneth L. Short 10 Type Declarations
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This note was uploaded on 08/30/2010 for the course ESE 382 taught by Professor Short during the Spring '10 term at SUNY Stony Brook.

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LEC-04 - 04 Signals and Data Types 1/16/2010 Signals and...

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