LEC-03 - 03 Entities, Architecture, and Coding Styles...

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Unformatted text preview: 03 Entities, Architecture, and Coding Styles Copyright 2005, 2006 Kenneth L. Short 1 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 1 Entities, Architectures, and Coding Styles Prof. Ken Short 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 2 Overview The simplest VHDL design description is a single design entity comprised of an entity declaration and an architecture body together in one source file. Alternative architecture bodies for the same entity declaration describe different ways of accomplishing the same function An architecture body can be written in one of three primary coding styles: dataflow, behavioral, or structural Once created, design entities can be used as components in more complex hierarchical systems. 03 Entities, Architecture, and Coding Styles Copyright 2005, 2006 Kenneth L. Short 2 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 3 Design Entity Primary hardware abstraction in VHDL Represents all or a portion of a hardware design Consists of an entity declaration and architecture body Separation of entity declaration from architecture body simplifies experimenting with alternative implementations Entity declaration describes system interface Architecture body describes system function or structure Entity Declaration (external view) Architecture Body (internal function) Design Entity 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 4 Entity Declaration Gives design entity a name Names entitys ports and defines the type and direction of transfer of data Provides all the information needed to connect a design entity into its environment 03 Entities, Architecture, and Coding Styles Copyright 2005, 2006 Kenneth L. Short 3 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 5 Entity Declaration Syntax entity identifier is [port ( port _interface_list ) ;] end [ entity ] [ entity _simple_name ] ; port _interface_list ::= [ signal ] identifier_list : [ mode ] subtype_indication [ := static _expression ] {; [ signal ] identifier_list : [ mode ] subtype_indication [ := static _expression ] } 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 6 Simplified Syntax Notations Meaning Symbol not supported by 1076.6 compliant synthesizers text ignored by 1076.6 compliant synthesizers text enclose repeated items. repeated zero or more times { } enclose optional items [ ] Separates alternative items | The text to the left of the symbol can be replaced by the text to the right of the symbol ::= 03 Entities, Architecture, and Coding Styles Copyright 2005, 2006 Kenneth L. Short 4 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 7 Half-Adder Entity Declaration entity half_adder is port (a, b : in std_logic; sum, carry_out: out std_logic); end half_adder; 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 8 IEEE VHDL Related Standards 03 Entities, Architecture, and Coding Styles Copyright 2005, 2006 Kenneth L. Short 5 1/16/2010 Copyright 2005, 2006 Kenneth L. Short 9 1076.6 Compliant Synthesizer1076....
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LEC-03 - 03 Entities, Architecture, and Coding Styles...

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