LEC-02 - 02 Introduction Part 2 1/11/2010 Design Flow for...

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02 Introduction Part 2 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 1 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 1 Design Flow for VHDL/PLD Design Methodology Compile Test Bench Functional Simulation Select PLD Synthesize Logic Post-Synthesis Simulation Place and Route Logic to Fit PLD Timing Simulation Verify PLD's Operation Progam PLD Analyze Requirements Develop Specification Write VHDL Test Bench Write VHDL Design Description Compile Design Description Part 1 of Design Flow Requirements Analysis Write (or Edit) VHDL Design Description Compile Design Description Functional Simulation Simulation Passed? Write (or Edit) VHDL Test Bench Compile Test Bench 2 1 1 Editor Editor Compiler Compiler Simulator VHDL design description source file compiled source file Yes No VHDL test bench source file compiled test bench file design phase tool legend functionally tested design description Develop Specification
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02 Introduction Part 2 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 2 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 3 Introduction Part 2 Ken Short 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 4 Overview ± In the previous class we looked at the first part of the VHDL/PLD design flow, which included functional simulation ± This class will continue with the VHDL/PLD design flow from that point to its completion
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02 Introduction Part 2 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 3 Part 2 of Design Flow Select Target PLD Synthesize Design Description Post Synthesis Simulation Simulation Passed? 3 2 1 Synthesizer Simulator target PLD selection synthesized logic Yes No compiled test bench file functionally tested design description Post Synthesis Simulation? Yes No EDIF post- synthesis netlist 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 6 PLD Selection ± In this course the term Programmable Logic Device (PLD) is used generically, it includes: ² Simple PLDs (SPLDs) ² Complex PLDs (CPLDs) ² Field Programmable Gate Arrays (FPGAs) ± Selection criteria include ± Logic capacity ± Speed ± Architecture ± Reprogrammability ± Cost ± Packaging
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02 Introduction Part 2 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 4 1/11/2010 © Copyright 2002, 2006 Kenneth L. Short 7 Simple PLDs (SPLDs) ± An array of AND gates followed by an array of OR gates ± Programmable interconnects determine the inputs to the AND and OR gates ± Logic capacities range from 20 to 200 gates ± PLA (Programmable Logic Array) ²
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LEC-02 - 02 Introduction Part 2 1/11/2010 Design Flow for...

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