MIPSDataPathIntroduction

MIPSDataPathIntroduction - Csci 211 Computer System...

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
Csci 211 Computer System Architecture Csci 211 Computer System Architecture – Datapath and Control Design – Datapath and Control Design – Appendixes A & B – Appendixes A & B Xiuzhen Cheng cheng@gwu.edu
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Outline Single Cycle Datapath and Control Design Pipelined Datapath and Control Design
Background image of page 2
The Big Picture The Five Classic Components of a Computer Performance of a machine is determined by: Instruction count; Clock cycle time; Clock cycles per instruction Processor design (datapath and control) will determine: Clock cycle time; Clock cycles per instruction Who will determine Instruction Count? Compiler, ISA Control Datapath Memory Processor Input Output
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
How to Design a Processor: Step by Step 1. Analyze instruction set => datapath requirements 1. the meaning of each instruction is given by the register transfers 2. datapath must include storage element for registers 3. datapath must support each register transfer 2. Select the set of datapath components and establish clocking methodology 3. Assemble the datapath meeting the requirements 4. Analyze the implementation of each instruction to determine the settings of the control points that effects the register transfer 5. Assemble the control logic --- Use MIPS ISA to illustrate these five steps!
Background image of page 4
Example: MIPS 0 r0 r1 ° ° ° r31 PC lo hi Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC Data types ? Format ? Addressing Modes? Memory Addressing? Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Control J, JAL, JR, JALR BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL 32-bit instructions on word boundary
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MIPS Instruction Format op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op target address 0 26 31 6 bits 26 bits All MIPS instructions are 32 bits long. 3 formats: R-type I-type J-type The different fields are: op : operation (“opcode”) of the instruction rs, rt, rd : the source and destination register specifiers shamt : shift amount funct : selects the variant of the operation in the “op” field address / immediate : address offset or immediate value target address : target address of jump instruction
Background image of page 6
MIPS Instruction Formats Summary Minimum number of instructions required Information flow: load/store Logic operations: logic and/or/not, shift Arithmetic operations: addition, subtraction, etc. Branch operations: Instructions have different number of operands: 1, 2, 3 32 bits representing a single instruction Disassembly is simple and starts by decoding opcode field. Comments Fields Name Arithmetic instruction format funct shamt rd rt rs op R-format All MIPS instructions 32 bits 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Field size Transfer, branch, imm. format address/immediate rt rs op I-format Jump instruction format target address op J-format
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MIPS Addressing Modes Register addressing Operand is stored in a register. R-Type
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 08/31/2010.

Page1 / 81

MIPSDataPathIntroduction - Csci 211 Computer System...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online