appxA - ECEn/CS 224 Appendix A Homework Solutions A.1...

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Last updated: 10/12/2006 ECEn/CS 224 Appendix A Homework Solutions A.1 Implement a 4:1 MUX using built-in gates. Draw the schematic of the corresponding circuit. module mux41(out, I0, I1, I2, I3, s0, s1); input I0, I1, I2, I3, s0, s1; output out; wire s0_not, s1_not, and_I0, and_I1, and_I2, and_I3; not(s0_not, s0); not(s1_not, s1); and(and_I0, I0, s0_not, s1_not); and(and_I1, I1, s0, s1_not); and(and_I2, I2, s0_not, s1); and(and_I3, I3, s0, s1); or(out, and_I0, and_I1, and_I2, and_I3); endmodule s0 s1 I0 I1 I2 I3 s0_not s1_not and_I0 and_I1 and_I2 and_I3 out
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Last updated: 10/12/2006 A.2. Implement a 2:4 decoder using built-in gates. Draw the schematic of the corresponding circuit. module decoder24 (O0, O1, O2, O3, I0, I1); input I0, I1; output O0, O1, O2, O3; wire I0_not, I1_not; not(I0_not, I0); not(I1_not, I1); and(O0, I0_not, I1_not); and(O1, I0, I1_not); and(O2, I0_not, I1); and(O3, I0, I1); endmodule I0 I1 I0_not I1_not O0 O1 O2 O3
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Last updated: 10/12/2006 A.3. Implement a 4:1 MUX using your 2:4 decoder and some built-in gates. Draw the schematic of the corresponding circuit. You can show the 2:4 decoder as a block in this schematic (no need to break it down to its constituent gates). module mux41_alt(out, I0, I1, I2, I3, s0, s1); input I0, I1, I2, I3, s0, s1; output out; wire dec0, dec1, dec2, dec3, and_I0, and_I1, and_I2, and_I3;
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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appxA - ECEn/CS 224 Appendix A Homework Solutions A.1...

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