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# appxB - ECEn/CS 224 Appendix B Homework Solutions B.1...

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Last updated: 10/24/2006 ECEn/CS 224 Appendix B Homework Solutions B.1 Implement a 4:1 MUX using a single dataflow assignment statement involving only concatenation, replication, and the operators for AND, OR, and NOT. module mux41(out, in0, in1, in2, in3, sel); input in0, in1, in2, in3; input [1:0] sel; output out; assign out = (in0 & (~sel[1]) & (~sel[0])) | (in1 & (~sel[1]) & sel[0] ) | (in2 & sel[1] & (~sel[0])) | (in3 & sel[1] & sel[0] ); endmodule B.2 Implement a 4:1 MUX using a single dataflow assignment statement and the ?: operator. module mux41(out, in0, in1, in2, in3, sel); input in0, in1, in2, in3; input [1:0] sel; output out; assign out = (sel == 2’b00)? in0 : (sel == 2’b01)? in1 : (sel == 2’b10)? in2 : in3; endmodule B.3 Repeat the previous 2 problems but parameterize your designs for any size operands. module mux41n_1(out, in0, in1, in2, in3, sel); parameter WID = 16; input [WID-1:0] in0, in1, in2, in3; input [1:0] sel; output [WID-1:0] out; assign out = (in0 & {WID{~sel[1]}} & {WID{~sel[0]}}) | (in1 & {WID{~sel[1]}} & {WID{ sel[0]}}) | (in2 & {WID{ sel[1]}} & {WID{~sel[0]}}) | (in3 & {WID{ sel[1]}} & {WID{ sel[0]}});

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