chap06 - zero . 6.7. Bubble match the schematic of Figure...

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Last updated: 10/1/2006 ECEn/CS 224 Chapter 6 Homework Solutions Figure 5.2(a) 6.1. Implement the schematic for Figure 5.2(a) using only NOR gates. 6.2. Implement the schematic for Figure 5.2(a) using only NAND gates. A’ B A C F A’ B A C F
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Last updated: 10/1/2006 6.5. Assume you have been given the assignment to design a function to determine whether the value of a 4-bit Boolean value is equal to zero. A 4-bit value is zero if all of its individual bits are zero. The output of this function should be TRUE when the value of the 4-bit value is zero. Draw a single-gate schematic which implements this function. Use the correct symbol and justify your answer. The output of this function is “1” if and only if all of the inputs are “0”. This is the correct symbol because it clearly suggests that the output is “1” when the first, second, third, and fourth inputs are all
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Unformatted text preview: zero . 6.7. Bubble match the schematic of Figure 6.14 to have a non-inverted output. Then, write the logic function the circuit implements by inspection. The bubble matched circuit with non-inverted output is: The logic function for this circuit is: F = (A’+B’)E + (C’ + D’) = (A’+B’)E + C’ + D’ A B E C D F Last updated: 10/1/2006 6.8. Bubble match the schematic of Figure 6.14 to have an inverted output. Then, write the logic function the circuit implements by inspection. F = [(AB + E’)(CD)]’ = [(AB + E’)CD]’ 6.9. Use DeMorgan’s to verify that your answers to the previous two problems are equivalent. F = [(AB + E’)CD]’ = (AB+E)’ + (CD)’ = (AB)’E’ + (C’ + D’) = (A’ + B’)E’ + C’ + D’ The final line is the expression we obtained in problem 6.7. Thus the two answers are equivalent. A B E C D F...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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chap06 - zero . 6.7. Bubble match the schematic of Figure...

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