Last updated: 10/10/2006
ECEn/CS 224
Chapter 10 Homework Solutions
10.1
The figure below is a detailed timing diagram for a NANDlike gate. If you were
interested in knowing how fast this gate would run for purposes of critical path analysis,
what would you use for
t
prop
? Why?
The critical path of the gate is the worst case delay and should be used for
t
prop
. In this
case, the worst case delay is 8 ns, thus
t
prop
= 8 ns.
10.2
If you were doing a more detailed timing analysis which separated out
t
proprise
and
t
prop
fall
, what would be reasonable values to use for each of these delays?
We use the worst case delay for each of these. The worst case for
t
proprise
is 3ns.
The
worst case for
t
propfall
is 8ns.
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Last updated: 10/10/2006
10.3.
Determine what the critical path is through circuit of Figure 10.15. To answer this
question, redraw the circuit for your answer and draw a heavy line along the critical path.
NOTE: inverters are often not drawn in schematics to simplify them. However, any
signal that is complemented (
A'
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 Spring '10
 Schultz
 Project Management, Gate, Critical path method, Delay, Program Evaluation and Review Technique, Tom DeLay

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