chap11 - Last updated: 10/18/2006 ECEn/CS 224 Chapter 11...

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Unformatted text preview: Last updated: 10/18/2006 ECEn/CS 224 Chapter 11 Homework Solutions 11.1 Below is a timing diagram for the SR latch of Figure 11.1. Fill in the output waveform. Reflect approximate timing. See section 11.7 to remind you what is meant by approximate timing . Figure 11.1: SR Latch Last updated: 10/18/2006 11.2 Repeat Problem 11.1 but with detailed timing. You may simply label each output signal transition in the timing diagram with the time it occurs. Delays of the various gates include: t NOT = 1 ns, t AND = 3 ns, t NOR = 2 ns . 11.3 Complete the timing diagram below for an SR latch. In this case, the circuit oscillates. Use t NOR = 2 ns and accurately reflect the Q and Q waveforms in the drawing (complete with timing). 10ns 12ns 14ns 30ns 32ns 34ns 80ns 82ns 90ns 92ns 100ns 5ns 5ns 7ns 15ns 15ns 17n 19n 21n 23n 25n 27n 29n 29ns 31n 33n 40ns Last updated: 10/18/2006 11.5 Shown in the figure below is a storage circuit made from NAND gates instead of NOR gates. Experiment with values on the S and R inputs to determine how it works. Hint: start with S = R =1. Write a transition table to summarize what you find....
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chap11 - Last updated: 10/18/2006 ECEn/CS 224 Chapter 11...

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