register_file - ECEn/CS 224 Register File Homework...

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Unformatted text preview: ECEn/CS 224 Register File Homework Solutions 1. Write the logic equation which describes the data out after the next clock cycle. It should be in the form Dout+ = (logic equation here) and should use Dout, DataIn, and Write as literals in the equation. Write 0 0 0 0 1 1 1 1 Din 0 0 1 1 0 0 1 1 Dout 0 1 0 1 0 1 0 1 Dout+ 0 1 0 1 0 0 1 1 Din, Dout Write 00 0 1 0 0 01 1 0 11 1 1 10 0 1 Dout+ = (DataIn • Write) + (Dout • Write’) Last updated: 10/19/2006 2. Using the symbol for the 1-bit register, design a 4-bit register. Note that within a register word, all bits are clocked and written by the same Clk and Write signals. Din[3] Din[2] Din[1] Din[0] Din W rite Clk Dout Din Write Clk Dout Din W rite Clk Dout Din W rite Clk Dout Write Clk Dout[3] Dout [2] Dout [1] Dout [0] 3. Design a 2:4 decoder using logic gates. Last updated: 10/19/2006 4. Design a 4-bit word by 4-word register file (4 registers of 4 bits each). You will use the 4-bit register symbols and the 2:4 decoder for register selection. The address inputs to the decoder will be the write address bits for your register file. The schematic is shown below. Notice that the inside of the decoder (the 4 AND gates on the left) are shown rather than a 2:4 decoder block. Also, this example deviates somewhat from the naming conventions used in the previous examples. Last updated: 10/19/2006 5. Now design the circuit that will accomplish the read. It needs to use the read address bits (register select address bits) to choose which group of 4 bits from the register file output should be selected as the DataOut signals. In essence what you need to design is a 4-bit, 4:1 multiplexer which selects among 4 groups of 4-bit data inputs. Pay close attention to the address bits and which data bits they are selecting. As you might guess, you should build this out of a collection of 4:1 multiplexers. Reg0[0] Reg1[0] Reg2[0] Reg3[0] I0 I1 I2 I3 sel Output[0] Reg0[1] Reg1[1] Reg2[1] Reg3[1] I0 I1 I2 I3 sel Output[1] Reg0[2] Reg1[2] Reg2[2] Reg3[2] I0 I1 I2 I3 sel Output[2] Reg0[3] Reg1[3] Reg2[3] Reg3[3] I0 I1 I2 I3 sel Output[3] Read Address Last updated: 10/19/2006 6. Draw a block diagram to show how all the pieces fit together to make a complete, dualported 4x4 register file. Data In Reg0[0] Reg1[0] Reg2[0] Reg3[0] I0 I1 I2 I3 sel Output[0] Write Address Clock Reg0[1] Reg1[1] Reg2[1] Reg3[1] I0 I1 I2 I3 sel Output[1] Reg0[2] Reg1[2] Reg2[2] Reg3[2] Register Write I0 I1 I2 I3 sel Output[2] Reg0[3] Reg1[3] Reg2[3] Reg3[3] I0 I1 I2 I3 sel Output[3] Read Address Last updated: 10/19/2006 ...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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