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Unformatted text preview: Physical Memory (DRAM) VP 1 PP 0
VP 2 VP 7 VP 4 Virtual address 1 1 0 0 0 0 PTE 7 1 PP 3 null Virtual Memory (disk)
VP 1 VP 2 VP 3 VP 4 VP 6 VP 7 Memory resident page table (DRAM) Figure 10.6: VM page fault (before). The reference to a word in VP 3 is a miss and triggers a page fault. The page fault exception invokes a page fault exception handler in the kernel, which selects a victim page, 492 CHAPTER 10. VIRTUAL MEMORY in this case VP 4 stored in PP 3. If VP 4 has been modiﬁed, then the kernel copies it back to disk. In either case, the kernel modiﬁes the page table entry for VP 4 to reﬂect the fact that VP 4 is no longer cached in main memory. Next the kernel copies VP 3 from disk to PP 3 in memory, updates PTE 3, and then returns. When the handler returns, it restarts the faulting instruction, which resends the faulting virtual address to the address translation hardware. But now, VP 3 is cached in main memory, and the page hit is handled normally by the address translation hardware, as we saw in Figure 10.5. Figure 10.7 shows the state of our example page table after the page fa...
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- Spring '10
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