366 relocation type r 386 32 absolute addressing 367

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Unformatted text preview: nd yourself complaining about the cramped 64-bit address space on your personal computer! # address bits (Ò) ½ ¿¾ ¾ # unique addresses (Æ ) ¾ ¾½ ¾ ½ ¾ à Largest address ¾½ ¾¿¾ ¾ ¾ ¾¿¾ ¾ ½ ½ ½ ¾ Ì ¿ È ¾ ½ ¾ Ô Ì ½ ½ ½ ½ ¿ ½ Ã È ¾ Problem 10.2 Solution: [Pg. 490] Ô Since each virtual page is È ¾ bytes, there are a total of each of which needs a page table entry (PTE). ¾ Ò ¾ Ò possible pages in the system, Ô Ò È ¾Ô 16 16 32 32 4K 8K 4K 8K # PTE’s 16 8 1M 512K Problem 10.3 Solution: [Pg. 500] You need to understand this kind of problem cold in order to understand address translation. Here is how to solve the first subproblem: We are given Ò ¿¾ virtual address bits and Ñ ¾ physical address bits. A page size of È ½Ã means we need ÐÓ ¾ ´½Ã µ ½¼ bits for both the VPO and PPO (Recall that the VPO and PPO are identical). The remaining address bits are the VPN and PPN respectively. È 1 KB 2 KB 4 KB 8 KB # VPN bits 22 21 20 19 # VPO bits 10 11 12 13 # PPN bits 14 13 12 11 # PPO bits 10 11 12 13 Problem 10.4 Solution: [Pg. 507] B.10. VIRTUAL MEMORY 731 Doing a few of these manual simulations is a great way to firm up your understanding of address translation. You might find it helpful to write out all the bits in the addresses, and then draw boxes around the different bit fields, such as VPN, TLBI, etc. In this particular problem, there are no misses of any kind: the TLB has a copy of the PTE and the cache...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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