process 1 virtual memory physical memory process 2

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Unformatted text preview: id 1 0 0 1 Tag 00 04 06 0A PPN – – – 34 VPO Valid 0 0 0 1 Tag 07 0A 03 02 PPN 02 – – – Valid 1 0 0 0 (a) TLB: Four sets, sixteen entries, four-way set associative. VPN 00 01 02 03 04 05 06 07 PPN 28 – 33 02 – 16 – – Valid 1 0 1 1 0 1 0 0 VPN 08 09 0A 0B 0C 0D 0E 0F PPN 13 17 09 – – 2D 11 0D Valid 1 1 1 0 0 1 1 1 (b) Page table: Only the first sixteen PTEs are shown. 11 Physical Address PPN Idx 0 1 2 3 4 5 6 7 8 9 A B C D E F Tag 19 15 1B 36 32 0D 31 16 24 2D 2D 0B 12 16 13 14 Valid 1 0 1 0 1 1 0 1 1 0 1 0 0 1 1 0 Blk 0 99 – 00 – 43 36 – 11 3A – 93 – – 04 83 – Blk 1 11 – 02 – 6D 72 – C2 00 – 15 – – 96 77 – Blk 2 23 – 04 – 8F F0 – DF 51 – DA – – 34 1B – PPO Blk 3 11 – 08 – 09 1D – 03 89 – 3B – – 15 D3 – 10 9 CT 8 CI 7 6 5 4 3 2 1 CO 0 (c) Cache: 16 sets, four-byte blocks, direct mapped. Figure 10.21: TLB, page table, and cache for small memory system. All values in the TLB, page table, and cache are in hexadecimal notation. 10.6. ADDRESS TRANSLATION TLBT 0x03 11 10 9 0 01 VPN 0x0f TLBI 0x03 76 11...
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