0 figure 637 line matching and word selection in a

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Unformatted text preview: parameters for a number of different caches. For each cache, determine the number of cache sets (Ë ), tag bits (Ø), set index bits (×), and block offset bits ( ). Cache 1. 2. 3. Ñ Ë Ø × 32 32 32 1024 1024 1024 4 8 32 1 4 32 6.4.2 Direct-Mapped Caches Caches are grouped into different classes based on , the number of cache lines per set. A cache with exactly one line per set ( ½) is known as a direct-mapped cache (see Figure 6.27). Direct-mapped 6.4. CACHE MEMORIES set 0: set 1: valid valid tag tag ••• set S-1: valid tag cache block cache block cache block 307 E=1 lines per set Figure 6.27: Direct-mapped cache ( ½ ). There is exactly one line per set. caches are the simplest both to implement and to understand, so we will use them to illustrate some general concepts about how caches work. Suppose we have a system with a CPU, a register file, an L1 cache, and a main memory. When the CPU executes an instruction that reads a memory word Û, it requests the word from the L1 cache. If the L1 cache has a cached copy of Û, then we have an L1 cache hit, and the cache quickly extracts Û and returns it to the CPU. Otherwise, we have a cache miss and the CPU must wait while the L1 cache requests a copy of the block containg Û from the main memory. When the requested...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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