0 int i for i 0 i 8 i sum xi yi return

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: lled compulsory misses or cold misses. Cold misses are important because they are often transient events that might not occur in steady state, after the cache has been warmed up by repeated memory accesses. Whenever there is a miss, the cache at level must implement some placement policy that determines where to place the block it has retrieved from level · ½. The most flexible placement policy is to allow any block from level · ½ to be stored in any block at level . For caches high in the memory hierarchy (close to the CPU) that are implemented in hardware and where speed is at a premium, this policy is usually too expensive to implement because randomly placed blocks are expensive to locate. Thus, hardware caches typically implement a more restricted placement policy that restricts a particular block at level · ½ to a small subset (sometimes a singleton) of the blocks at level . For example, in Figure 6.22, we might decide that a block at level · ½ must be placed in block ( mod 4) at level . For example, blocks 0, 4, 8, and 12 at level · ½ would map to block 0 at level ,...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online