1 load 1 load 2 load 11 1 01 load 1 load 2 load 11

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ycle counter. With the IA32 architecture, cycle counters were introduced in conjunction with the “P6” microarchitecture (the PentiumPro and its successors). The cycle counter is a 64-bit, unsigned number. For a processor operating with a 1 GHz clock, this counter will wrap around from ¾ ½ to ¼ only once every ½ ¢ ½¼½¼ seconds, or every 570 years. On the other hand, if we consider only the low order 32 bits of this counter as an unsigned integer, this value will wrap around every 4.3 seconds. One can therefore understand why the IA32 designers decided to implement a 64-bit counter. The IA32 counter is accessed with the rdtsc (for “read time stamp counter”) instruction. This instruction takes no arguments. It sets register %edx to the high-order 32 bits of the counter and register %eax to the low-order 32 bits. To provide a C program interface, we would like to encapsulate this instruction within a procedure: void access counter(unsigned *hi, unsigned *lo); This procedure should set location hi to the high-order 32 bits of the c...
View Full Document

Ask a homework question - tutors are online