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Unformatted text preview: 507 bit position VA = 0x03d4 13 0 12 0 8 1 5 0 4 1 32 01 VPO 0x14 1 0 0 0 To begin, the MMU extracts the VPN (0x0F) from the virtual address and checks with the TLB to see if has cached a copy of PTE 0x0F from some previous memory reference. The TLB extracts the TLB index (0x03) and the TLB tag (0x3) from the VPN, hits on a valid match in the second entry of Set 0x3, and returns the cached PPN (0x0D) to the MMU. If the TLB had missed, then the MMU would need to fetch the PTE from main memory. However, in this case we got lucky and had a TLB hit. The MMU now has everything it needs to form the physical address. It does this by concatenating the PPN (0x0D) from the PTE with the VPO (0x14) from the virtual address, which forms the physical address (0x354). Next, the MMU sends the physical address to the cache, which extracts the cache offset CO (0x0), the cache set index CI (0x5), and the cache tag CT (0x0D) from the physical address.
CT 0x0d 10 9 8 011 PPN 0x0d CI 0x05 432 101 PPO 0x14 CO 0x0 10 00 bit position PA = 0x354 11 0 7 0 6 1 5 0 Since the tag in Set 0x5 matches C...
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