12 repeat problem 610 for memory address 0x1fe4 a

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Unformatted text preview: -1: 0 valid tag cache block Figure 6.28: Set selection in a direct-mapped cache. Line Matching in Direct-Mapped Caches Now that we have selected some set in the previous step, the next step is to determine if a copy of the word Û is stored in one of the cache lines contained in set . In a direct-mapped cache, this is easy and fast because there is exactly one line per set. A copy of Û is contained in the line if and only if the valid bit is 308 CHAPTER 6. THE MEMORY HIERARCHY set and the tag in the cache line matches the tag in the address of Û. Figure 6.29 shows how line matching works in a direct-mapped cache. In this example, there is exactly one cache line in the selected set. The valid bit for this line is set, so we know that the bits in the tag and block are meaningful. Since the tag bits in the cache line match the tag bits in the address, we know that a copy of the word we want is indeed stored in the line. In other words, we have a cache hit. On the other hand, if either the valid bit were...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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