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# 13 t chilimbi m hill and j larus cache conscious

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Unformatted text preview: can really understand how caches work. Ñ Ë Ø × 1. 2. 3. 32 32 32 1024 1024 1024 4 8 32 1 4 32 256 32 1 22 24 27 8 5 0 2 3 5 Problem 6.7 Solution: [Pg. 312] The padding eliminates the conﬂict misses. Thus ¿ Problem 6.8 Solution: [Pg. 313] Sometimes, understanding why something is a bad idea helps you understand why the alternative is a good idea. Here, the bad idea we are looking at is indexing the cache with the high order bits instead of the middle bits. A. With high-order bit indexing, each contiguous array chunk consists of ¾Ø blocks, where Ø is the number of tag bits. Thus, the ﬁrst ¾Ø contiguous blocks of the array would map to Set 0, the next ¾Ø blocks would map to Set 1, and so on. B. For a direct-mapped cache where ´Ë Ñµ ´ ½¾ ½ ¿¾ ¿¾µ, the cache capacity is 512 32-byte blocks, and there are Ø ½ tag bits in each cache line. Thus, the ﬁrst ¾½ blocks in the array would map to Set 0, the next ¾½ blocks to Set 1. Since our array consists of only ¼...
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## This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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