3 if 1 and 2 then cache hit and block offset selects

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ul information, and Ø Ñ ´ · ×µ tag bits (a subset of the bits from the current block’s memory address) that uniquely identify the block stored in the cache line. 1 valid bit per line valid set 0: valid t tag bits per line tag tag 0 ••• 0 B = 2b bytes per cache block 1 1 ••• ••• B–1 E lines per set B–1 B–1 B–1 valid tag tag 0 ••• 0 ••• 1 1 ••• ••• S = 2s sets set 1: valid valid set S-1: valid tag tag 0 ••• 0 1 1 ••• ••• B–1 B–1 Cache size: C = B x E x S data bytes (a) t bits s bits b bits 0 Address: m-1 tag set index block offset (b) Figure 6.25: General organization of cache ´Ë ѵ. (a) A cache is an array of sets. Each set contains one or more lines. Each line contains a valid bit, some tag bits, and a block of data. (b) The cache organization induces a partition of the Ñ address bits into Ø tag bits, × set index bits, and block offset bits. In general, a cache’s organization can be characterized by the tuple ´Ë ѵ. The size (or capacity) of a cache, , is stated in terms of the aggregate size of all the blocks. The tag bi...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online