324_Book

# 30 s p harbison and g l steele jr c a reference manual

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: n memory 0 cache line 0 line 1 src 16 dst Figure B.1: Figure for Problem 6.14. Problem 6.14 Solution: [Pg. 324] A. The key to solving this problem is to visualize the picture in Figure B.1. Notice that each cache line holds exactly one row of the array, that the cache is exactly large enough to hold one array, and that for all , row of src and dst maps to the same cache line. Because the cache is too small to hold both arrays, references to one array keep evicting useful lines from the other array. For example, the write to dst[0][0] evicts the line that was loaded when we read src[0][0]. So when we next read src[0][1]we have a miss. 722 dst array col 0 col 1 row 0 m m row 1 m m APPENDIX B. SOLUTIONS TO PRACTICE PROBLEMS src array col 0 col 1 row 0 m m row 1 m h B. When the cache is 32 bytes, it is large enough to hold both arrays. Thus the only misses are the initial cold misses. dst array col 0 col 1 row 0 m h row 1 m h src array col 0 col 1 row 0 m h row 1 m h Problem 6.15 Solution: [Pg. 325] Each...
View Full Document

## This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online