5 edx5 addl jl i3 iteration 4 addl ecx5 load t6 incl

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Unformatted text preview: n that updates register Ö is decoded, a tag Ø is generated 224 CHAPTER 5. OPTIMIZING PROGRAM PERFORMANCE Operation Integer Add Integer Multiply Integer Divide Floating-Point Add Floating-Point Multiply Floating-Point Divide Load (Cache Hit) Store (Cache Hit) Latency 1 4 36 3 5 38 3 3 Issue Time 1 1 36 1 2 38 1 1 Figure 5.12: Performance of Pentium III Arithmetic Operations. Latency represents the total number of cycles for a single operation. Issue time denotes the number of cycles between successive, independent operations. (Obtained from Intel literature). giving a unique identifier to the result of the operation. An entry ´Ö ص is added to a table maintaining the association between each program register and the tag for an operation that will update this register. When a subsequent instruction using register Ö as an operand is decoded, the operation sent to the Execution Unit will contain Ø as the source for the operand value. When some execution unit completes the first operation, it generates a result ´Ú ص indicating that the operation with tag Ø...
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