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Unformatted text preview: called an L2 cache, between the L1 cache and the main memory, that can be accessed in a few clock cycles. The L2 cache can be attached to the memory bus, or it can be attached to its own cache bus, as shown in Figure 6.24. Some high-performance systems, such as those based on the Alpha 21164, will even include an additional level of cache on the memory bus, called an L3 cache, which sits between the L2 cache and main memory in the hierarchy. While there is considerable variety in the arrangements, the general principles are the same.
CPU chip register file L1 cache cache bus ALU system bus I/O bridge memory bus L2 cache bus interface Figure 6.24: Typical bus structure for L1 and L2 caches. 6.4. CACHE MEMORIES 305 6.4.1 Generic Cache Memory Organization
Ñ Consider a computer system where each memory address has Ñ bits that form Å ¾ unique addresses. × As illustrated in Figure 6.25(a), a cache for such a machine is organized as an array of Ë ¾ cache sets. Each set consists of cache lines. Each line consists of a data block of ¾ bytes, a valid bit that indicates whether or not the line contains meaningf...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.
- Spring '10
- The American