Acm may 1999 24 m w eichen and j a rochlis with

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Unformatted text preview: T CT CT CI CI CI CO CO B. Memory reference: Parameter Cache block offset (CO) Cache set index (CI) Cache tag (CT) Cache hit? (Y/N) Cache byte returned Value 0x1 0x5 0x6E N – B.6. THE MEMORY HIERARCHY Problem 6.12 Solution: [Pg. 318] Address: 0x1FF4 A. Address format (one bit per box): 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111100100 CT CT CT CT CT CT CT CT CI CI CI CO CO 721 B. Memory reference: Parameter Cache block offset Cache set index Cache tag Cache hit? (Y/N) Cache byte returned Value 0x0 0x1 0xFF N – Problem 6.13 Solution: [Pg. 318] This problem is a sort of inverse version of Problems 6.9–6.12 that requires you to work backwards from the contents of the cache to derive the addresses that will hit in a particular set. In this case, Set 3 contains one valid line with a tag of 0x32. Since there is only one valid line in the set, four addresses will hit. These addresses have the binary form 0 0110 0100 11xx. Thus, the four hex addresses that hit in Set 3 are: 0x064C, 0x064D, 0x064E, and 0x064F. mai...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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