After the disk controller receives the read command

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Unformatted text preview: h includes the memory controller), and the DRAM memory modules that comprise main memory. These components are connected by a pair of buses: a system bus that connects the CPU to the I/O bridge, and a memory bus that connects the I/O bridge to the main memory. CPU chip register file ALU system bus memory bus bus interface I/O bridge main memory Figure 6.6: Typical bus structure that connects the CPU and main memory. The I/O bridge translates the electrical signals of the system bus into the electrical signals of the memory bus. As we will see, the I/O bridge also connects the system bus and memory bus to an I/O bus that is shared by I/O devices such as disks and graphics cards. For now, though, we will focus on the memory bus. Consider what happens when the CPU performs a load operation such as movl A,%eax where the contents of address are loaded into register %eax. Circuitry on the CPU chip called the bus interface initiates a read transaction on the bus. The read transaction consists of three step...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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