Each pte in a level table contains either the ppn of

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Unformatted text preview: ll Virtual Memory (disk) VP 1 VP 2 VP 3 VP 4 VP 6 VP 7 Memory resident page table (DRAM) Figure 10.4: Page table. The example in Figure 10.4 shows a page table for a system with 8 virtual pages and 4 physical pages. Four virtual pages (VP 1, VP 2, VP 4, and VP 7) are currently cached in DRAM. Two pages (VP 0 and VP 5) have not yet been allocated, and the rest (VP 3 and VP 6) have been allocated but are not currently cached. An important point to notice about Figure 10.4 is that because the DRAM cache is fully associative, any physical page can contain any virtual page. Practice Problem 10.2: Determine the number of page table entries (PTEs) that are needed for the following combinations of virtual address size (Ò) and page size (È ). Ò È ¾Ô # PTEs 16 16 32 32 4K 8K 4K 8K 10.3.3 Page Hits Consider what happens when the CPU reads a word of virtual memory contained in VP 2, which is cached in DRAM (Figure 10.5). Using a technique we will describe in detail in Section 10.6, the address translation hardware uses the virtual address as an index to locate PTE 2 and read it from...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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