Figure 1029 highlights the kernel data structures

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Unformatted text preview: PA miss PTEA Processor VA MMU PA PA hit PTEA memory PA data data L1 Cache Figure 10.15: Integrating VM with a physically-addressed cache. VA: virtual address. PTEA: page table entry address. PTE: page table entry. PA: physical address. A TLB is a small, virtually-addressed cache where each line holds a block consisting of a single PTE. A TLB usually has a high degree of associativity. As shown in Figure 10.16, the index and tag fields that are used for set selection and line matching are extracted from the virtual page number in the virtual address. If Ø the TLB has Ì ¾ sets, then the TLB index (TLBI) consists of the Ø least significant bits of the VPN, and the TLB tag (TLBT) consists of the remaining bits in the VPN. n-1 p+t p+t-1 p p-1 0 TLB tag (TLBT) TLB index (TLBI) VPO VPN Figure 10.16: Components of a virtual address that are used to access the TLB. Figure 10.17(a) shows the steps involved when there is a TLB hit (the usual case). The key point here is that all of the address translation steps ar...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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