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Unformatted text preview: –” for “PPN” and leave parts C and D blank. Virtual address: 0x03d7 A. Virtual address format 13 12 11 10 9 8 7 6 5 4 3 2 1 0 508
B. Address translation Parameter Value VPN TLB index TLB tag TLB hit? (Y/N) Page fault? (Y/N) PPN C. Physical address format 11 10 9 8 7 D. Physical memory reference Parameter Byte offset Cache index Cache tag Cache hit? (Y/N) Cache byte returned Value CHAPTER 10. VIRTUAL MEMORY 6 5 4 3 2 1 0 10.7 Case Study: The Pentium/Linux Memory System
We conclude our discussion of caches and virtual memory with a case study of a real system: a Pentiumclass system running Linux. Figure 10.22 gives the highlights of the Pentium memory system. The Pentium has a 32-bit (4 GB) address space. The processor package includes the CPU chip, a uniﬁed L2 cache, and a cache bus (backside bus) that connects them. The CPU chip proper contains four different caches: an instruction TLB, data TLB, L1 i-cache, and L1 d-cache. The TLBs are virtually addressed. The L1 and L2 caches are physically addressed. All ca...
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- Spring '10
- The American