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# First notice that there is good temporal locality in

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Unformatted text preview: ndexing 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 set index bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Middle-Order Bit Indexing 313 4-set Cache 00 01 10 11 Figure 6.31: Why caches index with the middle bits. Practice Problem 6.8: In general, if the high-order × bits of an address are used as the set index, contiguous chunks of memory blocks are mapped to the same cache set. A. How many blocks are in each of these contiguous array chunks? B. Consider the following code that runs on a system with a cache of the form ´ ½¾ ½ ¿¾ ¿¾µ: int array[4096]; for (i = 0; i &lt; 4096; i++) sum += array[i]; What is the maximum number of array blocks that are stored in the cache at any point in time? ´Ë Ñµ 6.4.3 Set Associative Caches The problem with conﬂict misses in direct-mapped caches stems from the constraint that each set has exactly one line (or in our terminology, ½). A set associative cache relaxes this constraint so each set holds more than one cache line. A cache with ½ is often called an -way set associative cache....
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## This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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