For example a least frequently used lfu policy will

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Unformatted text preview: ts and valid bit are not included. Thus, Ë¢ ¢ . When the CPU is instructed by a load instruction to read a word from address of main memory, it sends the address to the cache. If the cache is holding a copy of the word at address , it sends the word immediately back to the CPU. So how does the cache know whether it contains a copy of the word at address ? The cache is organized so that it can find the requested word by simply inspecting the bits of the address, similar to a hash table with an extremely simple hash function. Here is how it works. 306 CHAPTER 6. THE MEMORY HIERARCHY The parameters Ë and induce a partitioning of the Ñ address bits into the three fields shown in Figure 6.25(b). The × set index bits in form an index into the array of Ë sets. The first set is set 0, the second set is set 1, and so on. When interpreted as an unsigned integer, the set index bits tell us which set the word must be stored in. Once we know which set the word must be contained in, the Ø tag bits in tell us which line (if any) in the set contains the word....
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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