For example applications that do intensive

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Unformatted text preview: base address unused G 0 D A CD WT U/S R/W P=1 Available for OS (page location in secondary storage) P=0 Field P R/W U/S WT CD A D G page base addr Description page is present in physical memory (1) or not (0) read-only or read/write access permission user/supervisor mode (kernel mode) access permission write-through or write-back cache policy for this page cache disabled or enabled reference bit (set by MMU on reads and writes, cleared by software) dirty bit (set by MMU on writes, cleared by software) global page (don’t evict from TLB on task switch) 20 most signicant bits of physical page address (b) Page Table Entry (PTE). Figure 10.25: Formats of Pentium page directory entry (PDE) and page table entry (PTE). of a PTE. When È ½, the address field contains a 20-bit physical page number that points to the base of some page in physical memory. Again, this imposes a 4-KB alignment requirement on physical pages. The PTE has two permission bits that control access to the page. The Ê Ï bit determines whether the contents of...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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