Unformatted text preview: e ﬁrst (lower-order) byte, DRAM 1 stores the next byte, and so on.
addr (row = i, col = j) : supercell (i,j)
DRAM 0 DRAM 7 64 MB memory module consisting of 8 8Mx8 DRAMs data bits 56-63 bits 48-55 bits 40-47 bits 32-39 bits 24-31 bits 16-23 bits 8-15 bits 0-7 63 56 55 48 47 40 39 32 31 24 23 16 15 87 0 Memory controller 64-bit double word at main memory address A 64-bit doubleword to CPU chip Figure 6.5: Reading the contents of a memory module. To retrieve a 64-bit doubleword at memory address , the memory controller converts to a supercell address ´ µ and sends it to the memory module, which then broadcasts and to each DRAM. In response, each DRAM outputs the 8-bit contents of its ´ µ supercell. Circuitry in the module collects these outputs and forms them into a 64-bit doubleword, which it returns to the memory controller.
1 IA32 would call this 64-bit quantity a “quadword.” 280 CHAPTER 6. THE MEMORY HIERARCHY Main memory can be aggregated by connecting multiple memory modules to the me...
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