For measures that relate to the capacity of drams and

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Unformatted text preview: s No Sensitive? No Yes Relative Cost 100X 1X Applications Cache memory Main mem, frame buffers SRAM DRAM Figure 6.2: Characteristics of DRAM and SRAM memory. Conventional DRAMs The cells (bits) in a DRAM chip are partitioned into supercells, each consisting of Û DRAM cells. A ¢ Û DRAM stores a total of Û bits of information. The supercells are organized as a rectangular array with Ö rows and columns, where Ö . Each supercell has an address of the form ´ µ, where denotes the row, and denotes the column. For example, Figure 6.3 shows the organization of a ½ ¢ DRAM chip with ½ supercells, Û bits per supercell, Ö rows, and columns. The shaded box denotes the supercell at address ´¾ ½µ. Information flows in and out of the chip via external connectors called pins. Each pin carries a 1-bit signal. Figure 6.3 shows two of these sets of pins: 8 data pins that can transfer one byte in or out of the chip, and 2 addr pins that carry 2-bit row and column supercell addresses. Other pins that carry...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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