For the small working set sizes along the l1 ridge

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Unformatted text preview: 164, put the L1 and L2 caches on the CPU chip and have an additional off-chip L3 cache. Modern processors include separate on-chip i-caches and d-caches in order to improve performance. With two separate caches, the processor can read an instruction word and a data word during the same cycle. To our knowledge, no system incorporates an L4 cache, although as processor and memory speeds continue to diverge, it is likely to happen. Aside: What kind of cache organization does a real system have? Intel Pentium systems use the cache organization shown in Figure 6.38, with an on-chip L1 i-cache, an on-chip L1 d-cache, and an off-chip unified L2 cache. Figure 6.39 summarizes the basic parameters of these caches. End Aside. Cache type on-chip L1 i-cache on-chip L1 d-cache off-chip L2 unified cache Associativity ( ) 4 4 4 Block size ( ) 32 B 32 B 32 B Sets (Ë ) 128 128 1024–16384 Cache size ( ) 16 KB 16 KB 128 KB–2 MB Figure 6.39: Intel Pentium cache organization. 6.4.7 Performance Impact of Cache Parameters Cache performance is evaluated with a number of metrics: ¯ ¯ ¯ ¯ Miss rate....
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