However many processes have identical read only text

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: f end-to-end address translation on a small system with a TLB and L1 d-cache. To keep things manageable, we make the following assumptions: ¯ ¯ ¯ ¯ ¯ ¯ ¯ The memory is byte addressable. Memory accesses are to 1-byte words (not 4-byte words). Virtual addresses are 14 bits wide (Ò Physical addresses are 12 bits wide (Ñ The page size is 64 bytes (È ). ½ ). ½¾ ). The TLB is four-way set associative with 16 total entries. The L1 d-cache is physically-addressed and direct mapped, with a 4-byte line size and 16 total sets. 10.6. ADDRESS TRANSLATION 505 Figure 10.20 shows the formats of the virtual and physical addresses. Since each page is ¾ bytes, the low-order six bits of the virtual and physical addresses serve as the VPO and PPO respectively. The high-order eight bits of the virtual address serve as the VPN. The high-order six bits of the physical address serve as the PPN. 13 Virtual Address VPN (Virtual Page Number) 11 Physical Address PPN (Physical Page Number) PPO (Physical Page Offset) 10 9 8 7 6 5 VPO (Virtual Page Offset) 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 Figure 10.20: Addressing for small memory system. Assume 14-bit virtual addresses (Ò phy...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online