Introduction memory interface io bridge main

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ses over the years, this processor-memory gap continues to increase. It is easier and cheaper to make processors run faster than it is to make main memory run faster. To deal with the processor-memory gap, system designers include smaller faster storage devices called caches that serve as temporary staging areas for information that the processor is likely to need in the near 10 CPU register file PC ALU system bus memory bus CHAPTER 1. INTRODUCTION Memory Interface I/O bridge main "hello,world\n" memory hello code I/O bus USB controller mouse keyboard graphics adapter display disk controller Expansion slots for other devices such as network adapters. "hello,world\n" disk hello executable stored on disk Figure 1.7: Writing the output string from memory to the display. future. Figure 1.8 shows the caches in a typical system. An L1 cache on the processor chip holds tens of CPU chip register file L1 cache cache bus ALU system bus memory bridge memory bus main memory (DRAM) L2 cache memory interface Figure 1.8: Caches. thousan...
View Full Document

Ask a homework question - tutors are online