Initially the heap consists of a single 16 word

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Unformatted text preview: N physical address of page base (if P=1) 12 PPO Physical address Figure 10.26: Pentium page table translation. Pentium TLB Translation Figure 10.27 summarizes the process of TLB translation in a Pentium system. If the PTE is cached in the set indexed by the TLBI (a TLB hit), then the PPN is extracted from this cached PTE and concatenated with the VPO to form the physical address. If the PTE is not cached, but the PDE is cached (a partial TLB hit), then 10.7. CASE STUDY: THE PENTIUM/LINUX MEMORY SYSTEM 513 the MMU must fetch the appropriate PTE from memory before it can form the physical address. Finally, if neither the PDE or PTE is cached (a TLB miss), then the MMU must fetch both the PDE and the PTE from memory in order to form the physical address. virtual address 20 12 CPU VPN 16 VPO 4 TLBT TLBI TLB hit TLB miss partial TLB hit PDE PTE 20 12 ... PPN PPO page table translation physical address Figure 10.27: Pentium TLB translation. 10.7.2 Linux Virtual Memory System A virtual memory system...
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