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Unformatted text preview: ins a store buffer containing the addresses and data of the store operations that have been issued to the store unit, but have not yet been completed, where completion involves updating the data cache. This buffer is provided so that a series of store operations can be executed without having to wait for each one to update the cache. When a load operation occurs, it must check the entries in the store buffer for matching addresses. If it ﬁnds a match, it retrieves the corresponding data entry as the result of the load operation. The assembly code for the inner loop, and its translation into operations during the ﬁrst iteration, is as follows: 258
%eax.0 %edx.0 CHAPTER 5. OPTIMIZING PROGRAM PERFORMANCE 1 2 3 4 5 6 7 ≠ store data store addr load
%edx.1a %edx.1b cc.1 decl jnc %eax.1 ≠ store addr load
cc.2 %eax.2 jnc incl Iteration 1 Cycle store data incl %edx.2b Iteration 2 Figure 5.35: Timing of write read for Example A. The store and load operations have different addresses, and so the load can...
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