Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ins a store buffer containing the addresses and data of the store operations that have been issued to the store unit, but have not yet been completed, where completion involves updating the data cache. This buffer is provided so that a series of store operations can be executed without having to wait for each one to update the cache. When a load operation occurs, it must check the entries in the store buffer for matching addresses. If it finds a match, it retrieves the corresponding data entry as the result of the load operation. The assembly code for the inner loop, and its translation into operations during the first iteration, is as follows: 258 %eax.0 %edx.0 CHAPTER 5. OPTIMIZING PROGRAM PERFORMANCE 1 2 3 4 5 6 7 ≠ store data store addr load %edx.1a %edx.1b cc.1 decl jnc %eax.1 ≠ store addr load %edx.2a decl cc.2 %eax.2 jnc incl Iteration 1 Cycle store data incl %edx.2b Iteration 2 Figure 5.35: Timing of write read for Example A. The store and load operations have different addresses, and so the load can...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online