Memory accesses are to 1 byte words not 4 byte words

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Unformatted text preview: memory. Since the valid bit is set, the address translation hardware knows that VP 2 is cached in memory. So it uses the physical memory 10.3. VM AS A TOOL FOR CACHING 491 address in the PTE (which points to the start of the cached page in PP 0) to construct the physical address of the word. Virtual address Physical page number or Valid disk address null PTE 0 0 Physical Memory (DRAM) VP 1 PP 0 VP 2 VP 7 VP 4 1 1 0 0 0 0 PTE 7 1 PP 3 null Virtual Memory (disk) VP 1 VP 2 VP 3 VP 4 VP 6 VP 7 Memory resident page table (DRAM) Figure 10.5: VM page hit. The reference to a word in VP 2 is a hit. 10.3.4 Page Faults In virtual memory parlance, a DRAM cache miss is known as a page fault. Figure 10.6 shows the state of our example page table before the fault. The CPU has referenced a word in VP 3, which is not cached in DRAM. The address translation hardware reads PTE 3 from memory, infers from the valid bit that VP 3 is not cached, and triggers a page fault exception. Physical page number or Valid disk address null PTE 0 0...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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