Notice that with 4 byte ptes each level 1 and level 2

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Unformatted text preview: a physical address. The operating system is responsible for maintaining the contents of the page table and transferring pages back and forth between disk and DRAM. Figure 10.4 shows the basic organization of a page table. A page table is an array of page table entries (PTEs). Each page in the virtual address space has a PTE at a fixed offset in the page table. For our purposes, we will assume that each PTE consists of a valid bit and an Ò-bit address field. The valid bit 490 CHAPTER 10. VIRTUAL MEMORY indicates whether the virtual page is currently cached in DRAM. If the valid bit is set, the address field indicates the start of the corresponding physical page in DRAM where the virtual page is cached. If the valid bit is not set, then a null address indicates that the virtual page has not yet been allocated. Otherwise, the address points to the start of the virtual page on disk. Physical page number or Valid disk address null PTE 0 0 1 1 0 0 0 0 PTE 7 1 Physical Memory (DRAM) VP 1 PP 0 VP 2 VP 7 VP 4 PP 3 nu...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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