Optimizing program performance data in eax x in ecx i

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Unformatted text preview: cycle 4 we can see that the machine is executing the addl for iteration 1; different parts of the load operations for iterations 2, 3, and 4; the jl for iteration 2; the cmpl for iteration 3; and the incl for iteration 4. Scheduling of Operations with Resource Constraints Of course, a real processor has only a fixed set of functional units. Unlike our earlier examples, where the performance was constrained only by the data dependencies and the latencies of the functional units, performance becomes limited by resource constraints as well. In particular, our processor has only two units capable of performing integer and branch operations. In contrast, the graph of Figure 5.15 has three of these operations in parallel on cycles 3 and four in parallel on cycle 4. Figure 5.17 shows the scheduling of the operations for combine4 with integer multiplication on a resourceconstrained processor. We assume that the general integer unit and the branch/integer unit can each begin a new operation on every clock cycle. It is possible to have more than two integer or branch operations executing i...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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