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Aside: A note on terminology. The storage community has never settled on a standard name for a DRAM array element. Computer architects tend to refer to it as a “cell”, overloading the term with the DRAM storage cell. Circuit designers tend to refer to it as a 278
DRAM chip CHAPTER 6. THE MEMORY HIERARCHY cols 0
2 / 1 2 3 0 1 rows 2 3 supercell (2,1) addr memory controller (to CPU)
8 / data internal row buffer Figure 6.3: High level view of a 128-bit ½ ¢ DRAM chip. “word”, overloading the term with a word of main memory. To avoid confusion, we have adopted the unambiguous term “supercell”. End Aside. Each DRAM chip is connected to some circuitry, known as the memory controller, that can transfer Û bits at a time to and from each DRAM chip. To read the contents of supercell ´ µ, the memory controller sends the row address to the DRAM, followed by the column address . The DRAM responds by sending the contents of supercell ´ µ back to the controller. The row address is called a RAS (Row Access Strobe) requ...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.
- Spring '10
- The American