So this assumption matches current trends another

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Unformatted text preview: ´ ½¾ µ 6.4. CACHE MEMORIES 309 In other words, the cache has four sets, one line per set, 2 bytes per block, and 4-bit addresses. We will also assume that each word is a single byte. Of course, these assumptions are totally unrealistic, but they will help us keep the example simple. When you are first learning about caches, it can be very instructive to enumerate the entire address space and partition the bits, as we’ve done in Figure 6.30 for our 4-bit example. There are some interesting things Address (decimal equivalent) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tag bits (Ø ½) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Address bits Index bits Offset bits (× ¾) ( ½) 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 Block number 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Figure 6.30: 4-bit address for example direct-mapped cache to notice about this enumerated space. ¯ ¯ ¯ The concatenation of the tag and index bits uniquely identifies each block in memory. For example, block 0 consists of addre...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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