This preview shows page 1. Sign up to view the full content.
Unformatted text preview: pages it out to disk. Step 6: The fault handler pages in the new page and updates the PTE in memory. Step 7: The fault handler returns to the original process, causing the faulting instruction to be restarted. The CPU resends the offending virtual address to the MMU. Because the virtual page is now cached in physical memory, there is a hit, and after the MMU performs the steps in Figure 10.14(b), the main memory returns the requested word to the processor Practice Problem 10.3:
Given a 32-bit virtual address space and a 24-bit physical address, determine the number of bits in the VPN, VPO, PPN, and PPO for the following page sizes È :
È # VPN bits # VPO bits # PPN bits # PPO bits 1 KB 2 KB 4 KB 8 KB 10.6.1 Integrating Caches and VM
In any system that uses both virtual memory and SRAM caches, there is the issue of whether to use virtual or physical addresses to access the cache. Although a detailed discussion of the tradeoffs is beyond our scope, most systems opt for physical addressing. Wit...
View Full Document