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Unformatted text preview: related to timing, that are important to hardware designers, but are beyond our scope. For your reference, Figure 10.12 summarizes the symbols that we will using throughout this section. Formally, address translation is a mapping between the elements of an (VAS) and an Å -element physical address space (PAS), MAP: VAS PAS Æ -element virtual address space 498 where MAP(A) CHAPTER 10. VIRTUAL MEMORY ¼ if data at virtual addr
if data at virtual addr is present at physical addr ¼ in PAS. is not present in physical memory. Figure 10.13 shows how the MMU uses the page table to perform this mapping. A control register in the CPU, the page table base register (PTBR) points to the current page table. The Ò-bit virtual address has two components: a Ô-bit virtual page offset (VPO) and an ´Ò Ôµ-bit virtual page number (VPN). The MMU uses the VPN to select the appropriate PTE. For example, VPN 0 selects PTE 0, VPN 1 selects VPN 1, and so on. The corresponding physical address is the concatenation of the...
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