This preview shows page 1. Sign up to view the full content.
Unformatted text preview: ly-addressed L1 caches have 128 sets and 32-byte cache blocks, each physical address has ﬁve ( ¾ ) cache offset bits and seven ) index bits. These 12 bits ﬁt exactly in the VPO of a virtual address, which is no accident! When the CPU (¾ needs a virtual address translated, it sends the VPN to the MMU and the VPO to the L1 cache. While the MMU is requesting a page table entry from the TLB, the L1 cache is busy using the VPO bits to ﬁnd the appropriate set and read out the four tags and corresponding data words in that set. When the MMU gets the PPN back from the TLB, the cache is ready to try to match the PPN to one of these four tags. ÐÓ ½¾ ÐÓ ¿¾ This suggests the following question for you to ponder: What options do Intel engineers have if they want to increase the L1 cache size in future systems and still be able to use this trick? End Aside. Pentium Page Tables
Every Pentium system uses the two-level page table shown in Figure 10.24. The level-1 table, known as the page directory, contains 1024 32-bit page directory entries (PDEs), each of which points to one of 1024 level-2 page...
View Full Document
- Spring '10
- The American