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Unformatted text preview: not set or the tags did not match, then we would have had a cache miss.
=1? (1) The valid bit must be set
0 1 2 3 4 5 6 7 selected set (i): 1 0110 w0 w1 w2 w3 (2) The tag bits in the cache =? line must match the tag bits in the address t bits 0110 tag s bits b bits i 100 set index block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte.
0 m-1 Figure 6.29: Line matching and word selection in a direct-mapped cache. Within the cache block, denotes the low-order byte of the word Û, Û½ the next byte, and so on. Û¼ Word Selection in Direct-Mapped Caches
Once we have a hit, we know that Û is somewhere in the block. This last step determines where the desired word starts in the block. As shown in Figure 6.29, the block offset bits provide us with the offset of the ﬁrst byte in the desired word. Similar to our view of a cache as an array of lines, we can think of a block as an array of bytes, and the byte offset as an index into that array. In the example, the...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.
- Spring '10
- The American